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AN-6846
Applying SG6846 to Control a Flyback Power Supply with Surge Current Output
Summary
This application note describes a detailed design strategy for a high-efficiency, compact flyback converter. Design considerations, mathematical equations, and guidelines for printed circuit board layout are presented.
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-frame SMPS SMPS with Surge-current Output, such as for Printers, Scanners, Motor Drivers
Figure 1. Pin Configuration
RI 4 0.9V/0.7V
VDD
VIN
3
Over-Power Compensation 1.18-0.08 XVIN
Soft Driver
8
GATE
VD D -TH-G VDD 7
UVLO Internal BIAS
Q
S R
OSC
Green Mode
6V
3R 16.5V/10.5V + 1R
R
2
FB
Latch
Slope Compensation Blanking Circuit
6
SENSE
23.6V
1R Debounce OCP Delay
IRT
RT 5
1.05V
1R /2R
1.15V 1 GND
Figure 2. Block Diagram
(c) 2008 Fairchild Semiconductor Corporation Rev. 1.3.2 * 9/26/08
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AN-6846
APPLICATION NOTE
Table 1. Comparison
Symbol
Feedback Input Section tD-OLP
Parameter
SG6846A
SG6846B
SG6846C SG6846G
Delay Time for Open-Loop Protection (RI = 26k)
1700ms
NA
110ms
Over-Temperature Protection (OTP) Section tDOTP-LATCH Over-Temperature Latch-off Debounce (RI = 26k) 100ms 100s
Current Sense Section tD-SCP tD-OCP VSTH (VIN=1V) VSTH (VIN=3V) VSTH - 2/3 (1/2) Delay Time for output short circuit protection (RI = 26k) Delay Time for Over-Current Protection (RI = 26k) Threshold Voltage for Current Limit Threshold Voltage for Current Limit Threshold Voltage for Over Current Protection 100ms 1700ms 0.83V 0.7V VSTH x 2/3 7ms 200ms NA 110ms 1.1V 0.94V VSTH x 1/2
Symbol
Oscillator Section VFB-N VFB-G VFB-ZDC
Parameter
SG6846A/B/C
SG6846G
FB Threshold Voltage For Frequency Reduction (RI = 26k) FB Voltage at Green-mode Minimum Frequency (RI = 26k) FB Threshold Voltage for Zero-duty
2.1 1.6 VFB-G
2.8V 2.3V 2V
Figure 3. SG6846A/B/C PWM Frequency
Figure 4. SG6846G PWM Frequency
(c) 2008 Fairchild Semiconductor Corporation Rev. 1.3.2 * 9/26/08
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AN-6846
APPLICATION NOTE
Description
The SG6846 is a highly integrated PWM controller IC that provides special features satisfying the needs for low standby power consumption. It also incorporates multiple protection functions. With low start-up current and low operating current, high-efficiency power conversion is achieved. The typical start-up current is only 8A and the operating current is around 3.7mA. In nominal loading conditions, the SG6846 operates at a fixed PWM frequency. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency under lightload conditions. Under no-load conditions, the power supply enters burst-mode. Green mode dramatically cuts the power loss at no-load and light-load conditions, enabling the power supply to meet stringent power conservation requirements. The SG6846 is specially designed for SMPS with surgecurrent output, incorporated with a two-level OCP function. Besides the cycle-by-cycle current limiting; if the switching current is higher than OCP threshold for a delay time, overcurrent protection is activated such that the SG6846 is totally shutdown. Other protection functions include AC input brownout protection with hysteresis and VDD overvoltage protection. For over-temperature protection, an external NTC thermistor can be applied to sense the ambient temperature. When OCP, VDD OVP, or OTP are activated, an internal latch circuit is used to latch-off the controller. If the latch circuit is triggered by over-temperature conditions, it resets when the temperature cools off sufficiently (SG6846CX) or when the AC supply is disconnected (SG6846LX). When the latch is triggered by VDD overvoltage conditions, the latch resets only when the AC supply is disconnected. Other features of this controller include built-in synchronized slope compensation and proprietary internal compensation for constant output power limit over universal AC input range. The gate output is clamped at 18V to protect the external MOSFET from over-voltage damage. practical. As the voltage of VDD reaches the startup threshold voltage VTH-ON, the SG6846 activates and drives the entire power supply. The IC then operates based on the auxiliary winding energy. Using one startup resistor (510K) with a 10F/50V holdup capacitor C1 can satisfy the three-second maximum power-on delay requirement in most applications. After startup, the energy is supplied from C2. The capacitance at VDD must be large enough to hold VDD above the off threshold voltage, VTH-OFF, at a step change of load. When an output short circuit occurs, the duration before VDD drops to below the off threshold voltage must be longer than the OCP delay time or it fails to trigger the internal latch circuit. A 100F/50V capacitor is suggested for C2.
Figure 6. Circuit Providing Power
The maximum power dissipation of RIN is:
PRIN,max
2 V AC,max
2 x RIN
(1)
where VAC,max is the maximum rectified input voltage. Taking a wide-range input (90VAC-264VAC) as an example, VAC,max =264V:
PRIN,max = 264 2 2 x 510 x 10 3 68mW
RI
(2)
RI
SG6846
In addition to the low startup current, SG6846 consumes less operating current than a traditional UC384x.
GND
Oscillator and Green-Mode Operation
Resistor RI programs the frequency of the internal oscillator. A 26 resistor RI determines PWM frequency as 65kHz:
fPWM (kHz ) = 1690 RI (k )
Figure 5. Setting PWM Frequency
(3)
Startup Circuitry
When the power is turned on, the input voltage charges the hold-up capacitor C1 via the startup resistors. As shown in Figure 2, one or two resistors from the AC utility are both
(c) 2008 Fairchild Semiconductor Corporation Rev. 1.3.2 * 9/26/08 3
A PWM frequency range of between 47kHz ~ 109kHz is recommended.
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AN-6846
APPLICATION NOTE
The proprietary green mode provides off-time modulation to reduce the PWM frequency at light-load and no-load conditions. The feedback voltage of the FB pin is taken as a reference. As shown in Figure 7, when the feedback voltage is lower than about 2.1V, the PWM frequency decreases. Because most losses in a switching-mode power supply are proportional to the PWM frequency, the off-time modulation reduces the power consumption of the power supply at lightload and no-load conditions. For a typical case of RI=26K, the PWM frequency is 65kHz at nominal load and decreases to 22.5kHz at light loads, about one third of the nominal PWM frequency. The power supply enters burst mode at zero-load conditions.
Built-in Slope Compensation
A flyback converter can be operated in discontinuous current mode (DCM) or continuous current mode (CCM). With the same output power, a converter in CCM exhibits smaller peak inductor current than in DCM. Therefore, a small-sized transformer and a low-rating MOSFET can be applied. On the secondary side of the transformer, the rms output current of DCM can be up to twice that of CCM. Larger wire gauge and output capacitors with larger ripple current ratings are required. DCM operation also results in higher output voltage spikes. A large LC filter has to be added. Therefore, a flyback converter in CCM achieves better performance with lower component cost. Despite the above advantages of CCM operation, there is one concern - stability. In CCM operation, the output power is proportional to the average inductor current, while the peak current is controlled. This causes the well-known subharmonic oscillation when the PWM duty cycle exceeds 50%. Adding slope compensation (reducing the current-loop gain) is an effective way to prevent oscillation. The SG6846 introduces a synchronized positive-going ramp (VSLOPE) in every switching cycle to stabilize the current loop. Therefore, the SG6846 enables design of a cost-effective, highly efficient, compact flyback power supply operating in CCM without adding external components. The positive ramp added is:
VSLOPE = VSL D
Figure 7. PWM Frequency vs. FB Voltage
FB Input
The SG6846 is designed for peak-current-mode control. A current-to-voltage conversion is accomplished externally with current-sense resistor RS. Under normal operation, the FB level controls the peak inductor current:
I pk = VFB - 1.2 4 .2 R S
(6)
(4)
where VFB is the voltage of FB pin. When VFB is less than 1.6V, the SG6846 terminates the output pulses. 0 is a typical feedback circuit mainly consisting of a shunt regulator and an opto-coupler. R1 and R2 form a voltage divider for output voltage regulation. R3 and C1 are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB= 47, CFB= 1nF) placed from the FB pin to GND can increase stability substantially. The maximum source current of the FB pin is about 2mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of the biasing resistor, Rb, is determined as:
Vo - VD - VZ K 2mA Rb
Figure 8. Feedback Circuit
where VSL = 0.33V and D = duty cycle.
(5)
where: VD is the drop voltage of photodiode, about 1.2V; VZ is the minimum operating voltage, 2.5V of the shunt regulator; and K is the current transfer rate (CTR) of the opto-coupler. For an output voltage VO=5V, with CTR=100%, the maximum value of Rb is 650.
(c) 2008 Fairchild Semiconductor Corporation Rev. 1.3.2 * 9/26/08 4
Figure 9. Synchronized Slope Compensation
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AN-6846
APPLICATION NOTE
Leading-Edge Blanking (LEB)
A voltage signal proportional to the MOSFET current develops on the current-sense resistor RS. Each time the MOSFET is turned on, a spike induced by the diode reverse recovery and by the output capacitances of the MOSFET and diode, appears on the sensed signal. A leading-edge blanking time (about 360ns) is introduced to avoid premature termination of the MOSFET by the spike. Therefore, only a small-value RC filter (e.g. 100 + 470pF) is required between the SENSE pin and RS. A non-inductive resistor for RS is recommended.
As the current-sense signal of the SENSE pin exceeds the internal limit VSENSE, 0.9V typically, the SG6846 stops the PWM pulses immediately. The output power of a flyback power supply in DCM is calculated as:
POUT = 1 2 L I pk fS 2
(7)
where: L is the inductance; Ipk is the peak inductor current; fs is the PWM frequency; and is the conversion efficiency. If the conversion efficiency remains unchanged for a wide input voltage range, the maximum output power would be the same for a fixed Ipk, which is limited by the internal current limiting threshold voltage VTH and RS. However, due to the time delay from the comparator to output stage inside the SG6846, the maximum output power with high line input is always higher than with low line. A 30% error is common for the universal input voltage range if the converter is operated in DCM. In CCM operation, the deviation becomes even worse. For the purpose of constant output power limit, the peak current limit VTH must be adjustable according to the input voltage. In the SG6846, the peak-current threshold is adjusted by the voltage of the VIN pin for constant output power limit over universal input-voltage range. Since the VIN pin is connected to the rectified AC input line voltage through the resistive divider, a higher line voltage generates a higher VIN voltage. The threshold voltage decreases as the VIN voltage increases, making the maximum output power at high line input voltage equal to that at low line input.
RS
Figure 10. Turn-on Spike
Output Driver / Soft Driving
The output stage is a fast totem-pole gate driver capable of directly driving external MOSFETs. An internal Zener diode clamps the driver voltage under 18V to protect MOSFETs against over voltage. By integrating circuits to control the slew rate of switch-on rising time, the external resistor RG may not be necessary to reduce switching noise, thereby improving EMI performance.
Figure 12. Universal Line Voltage Compensation for Constant Output Power Limit
Brownout Protection
Since the VIN pin is connected through a resistive divider to the rectified AC input line voltage, it can also be used for brownout protection. If the VIN voltage is less than 0.7V, the PWM output shuts off. As the VIN voltage reaches 0.9V, the PWM output is turned on again. The hysteresis window for on/off is around 0.2V. The recommended values for R1, R2, and C1 are 2M (1M+1M), 16.2K, and 4.7F. Using these values in the evaluation board, the power supply is turned off at 75V (max. load) / 64V (min. load) and recovered at 82V.
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Figure 11. Gate Driver
Constant Output Power Limit
The maximum output power of a flyback converter can be designed by the current-sense resistor RS. When the load increases, the peak inductor current increases accordingly.
(c) 2008 Fairchild Semiconductor Corporation Rev. 1.3.2 * 9/26/08
AN-6846
APPLICATION NOTE
Thermal Protection
A constant current, IRT, is provided from the pin RT. The resistor connected to pin RI determines its magnitude: IRT = 1.8V / RI For example, IRT = 70A if RI = 26K. For over-temperature protection (OTP), an NTC thermistor RT in series with a resistor Ra can be connected between the RT pin and ground. When the voltage of the RT pin drops below 1.065V, PWM output is latched off. A debounce time around 100s is added to prevent false triggering. After the latch is reset and cleared (SG6846CX: VRT>1.165V; SG6846LX: AC unplugged), PWM turns on again. If the RT pin is not used, connect a 100k resistor between the RT pin and ground to disable this thermal protection function. Beside NTC and Ra, a capacitor should be connected to RT pin to eliminate switching noise. This capacitor's value is less than 1nF (shown as Figure 14). (8)
Figure 13. Universal Line Voltage Compensation for Constant Output Power Limit
Two-level Over-Current Protection (OCP)
The cycle-by-cycle current limiting shuts down the PWM immediately when the switching current is over the peakcurrent threshold. In addition, an over-current protection circuit is built-in. When the switching current is higher than the OCP threshold, the internal counter starts counting up. When the switching current is lower than the OCP threshold, the internal counter counts down. When the total accumulated counting time is more than OCP delay time (SG6846A: 1600ms; SG6846C: 110ms), the controller is latched off. By adjusting the RS resistance to let the peak-current at maximum load under OCP threshold and over this threshold at peak load condition, the two-level OCP protection is enabled. These functions are especially designed for an SMPS with surge current output, such as for printers, scanners, and motor drivers.
Figure 15. T C1 (<1nF) Connect to RT Pin
Lab Note
Before rework or solder/desolder on the power supply, discharge the primary capacitors by an external bleeding resistor. Otherwise, the PWM IC may be destroyed by external high voltage during solder/desolder.
Figure 14. Timing Chart for Two-level Over-Current Protection (OCP)
This device is sensitive to ESD discharge. To improve production yield, the production line should be ESD protected according to ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents the controller from over-voltage destruction. The VDD voltage rises when an open-loop failure occurs. Once the VDD voltage exceeds 23.6V for around 100s, the power supply latches off.
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AN-6846
APPLICATION NOTE
Printed Circuit Board (PCB) Layout
High-frequency switching current/voltage makes PCB layout a very important design issue. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge/ESD tests. Guidelines: To get better EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor C1 first, then to the switching circuits. The high-frequency current loop is in C1 - Transformer - MOSFET - RS - C1. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 41) short, direct, and wide. High-voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, connect this heatsink to ground. As indicated by 3, the ground of control circuits should be connected first, then to other circuitry. As indicated by 2, the area enclosed by transformer auxiliary winding, D1, C2, D2, and C3 should also be kept small. Place C3 close to the SG6846 for good decoupling. Two suggestions with different pro and cons for ground connections are offered: GND3 2 4 1: This could avoid common impedance interference for sense signal. GND3214: This could be better for ESD testing where the earth ground is not available on the power supply. Regarding the ESD discharge path, the charges go from secondary through the transformer stray capacitance to GND2 first. The charges then go from GND2 to GND1 and back to the mains. Note that control circuits should not be placed on the discharge path. Point discharge for common choke can decrease high-frequency impedance and help increase ESD immunity. Should a Y-cap between primary and secondary be required, connect this Y-cap to the positive terminal of C1. If this Y-cap is connected to the primary GND, it should be connected to the negative terminal of C1 (GND1) directly. Point discharge of this Y-cap also helps for ESD. However, the creepage between these two pointed ends should be large enough to satisfy the requirements of applicable standards.
Figure 16. Layout Considerations
(c) 2008 Fairchild Semiconductor Corporation Rev. 1.3.2 * 9/26/08
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AN-6846
APPLICATION NOTE
Related Datasheets
SG6846 -- Highly Integrated Green-Mode PWM Controller SG6846A -- Highly Integrated Green-Mode PWM Controller SG6846B -- Highly Integrated Green-Mode PWM Controller SG6846C -- Highly Integrated Green-Mode PWM Controller SG6846G -- Highly Integrated Green-Mode PWM Controller
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